1. Field of the Invention
The present invention relates generally to non-semiconductor electrical and electronic elements used in printed circuit board applications and particularly to an improved package and method of packaging microminiature electronic components.
2. Description of Related Technology
Dual in-line chip carrier packages (DIPs) are well known in the field of electronics. A common example of a DIP is an integrated circuit, which is typically bonded to a ceramic carrier and electrically connected to a lead frame providing opposed rows of parallel electrical leads. The integrated circuit and ceramic carrier are normally encased in a black, rectangular plastic housing from which the leads extend.
The continuing miniaturization of electrical and electronic elements and high density mounting thereof have created increasing challenges relating to electrical isolation and mechanical interconnection. In particular, substantial difficulty exists in establishing reliable and efficient connections between fine gauge (AWG24 to AWG50) copper wire leads associated with various electronic elements within a given DIP. Presently known interconnect methods severely limit the ability to provide dense and reliable electrical connections or electrical isolation of such leads from DIP egress terminals.
One common prior art approach to electrically interconnecting two or more element leads is to manually form the connection or joint by twisting the wires together. The joint may then be individually soldered or sealed to make the connection more permanent. This technique requires significant labor in that each connection must be manually formed and soldered. Furthermore, such an arrangement requires space that is not always available in such microminiature packages, and often does not allow adequate electrical separation for the comparatively high voltages that may be carried in the circuit and the egress terminals. Another problem with this approach is that element leads are frequently broken or sheared during the subsequent package encapsulation process since they are not adequately captured or protected. The leads may also break as the result of thermal expansion and contraction.
A second prior art method of connecting element leads to the leadframe terminals (or interconnecting the leads of two or more electronic elements) is disclosed in U.S. Pat. No.5,015,981, which is illustrated herein as FIG. 1. This method involves routing the lead(s) 2 to an unused leadframe slot 3 located at the edge of the non-conducting base member 10, as shown in FIG. 1. Each of these slots is designed to receive a single conductive leadframe egress terminal element 4, which when assembled asserts an inward bias on the package thereby forcing contact between the conductive terminal element 4 of the leadframe and the electronic element lead(s) 2. However, this method suffers many of the same disabilities as the method previously described, since the wires must be routed to the edge of the package in proximity to the egress terminals. Such an arrangement also makes the connections susceptible to capacitive coupling or field effects relating to the egress terminals.
A third approach to solving these problems is set forth in U.S. Pat. No. 5,455,741, which discloses a wire-lead through hole interconnect device used for packaging electronic components. As shown in the aforementioned patent and FIGS. 2 and 3 herein, this device is characterized by a non-conductive base 10 with one or more component cavities 6, a plurality of through-holes 15 penetrating the thickness of the base in proximity to the cavities, and recesses 7 at the lower ends of the through holes to receive both electrically conductive printed circuit strips 8 and the solder joint 50 formed between the lead and the conductive strip. Electrical connection between the egress terminals of the package and the component leads 22 is provided by, inter alia, a conductive strip running 9 from the aforementioned solder joint outward around the edge or periphery of the base. This through-hole design provides a flat, "bump-free" bottom surface of the device, and aids the manufacturing and assembly process by allowing greater repeatability and reliability of component placement and joint formation, while reducing the required labor. It also permits the connection between the leads and the egress terminals to be formed more reliably. However, interconnection of the leads from various elements within the device is accomplished through use of the aforementioned conductive strips 8. Hence, to interconnect two electronic element leads, the presence of 1) a second through-hole; 2) a conductive strip; and 3) the recess necessary to receive the conductive strip and the soldered leads is required. Furthermore, two solder joints are required. Similarly, to connect three leads together, three through-holes and three solder joints are required.
It would therefore be desirable to provide a method of connecting two or more of such leads using a single solder joint, such a method furthermore allowing the soldering of all such joints simultaneously in one process step. This would not only save space within the package, but would also eliminate the labor and materials associated with forming the recess(es), installing the printed circuit elements, and soldering each lead individually. Ideally, these joints would be located internally within the package and away from the leadframe elements to minimize any capacitive or electrical interaction between the leads and the egress terminals and to minimize the length of wire runs required to make the connection.
In addition to the foregoing problems associated with lead/lead interconnection, electronic component placement within the package is of concern. The placement of various components is critical from the standpoint of electrical separation (i.e., reducing the interaction of localized electric and magnetic fields emanating from the elements), manufacturing repeatability and reduced labor costs, and device reliability. Heretofore, the placement of electronic elements within the package has been primarily dictated by physical considerations such as reducing the profile or dimensions of the package, and not necessarily with regard to the aforementioned factors. For example, the toroidal coil placement disclosed in the prior art interconnect devices does not specifically address electric or magnetic field interaction, the minimization of wire run length, or physical separation of the elements. Hence, it would be desirable to provide a package design which incorporates both an improved method of lead interconnection as previously described, and improved component placement.